a a techfocus media publication :: May 18, 2004 :: volume III, no. 7 a FROM THE EDITOR This week the embedded processor race gets really interesting as Altera announces Nios II . FPGAs are an excellent platform for implementation of flexible, low-cost, high-performance embedded systems and new products like Nios II threaten to start the revolution. We also have a contributed article from Andrew Kahng comparing FPGA, ASIC and the new structured ASIC fabrics. With several vendors surfing the void between FPGA and cell-based ASIC with middle-ground structured ASIC offerings, here's what you need to know about the tradeoffs between the technologies. Also, we were caught with our quiescent facts out of order on our " From Gordon to Geoffrey " article. Xilinx Principal Engineer, Austin Lesea, wrote in to remind us that 90nm FPGAs really don't use more power-per gate than previous generations. While leakage current may be higher, dynamic power consumption is still improved, and overall a device of equivalent density will burn less, not more juice than a similar 130nm device. Between the higher gate count (causing overall power to rise, although less than proportional with gate count) and the leakage current issue, we leapt like lemmings into the popular misconception. Nostrum Culpa. Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com Kevin Morris - Editor FPGA and Programmable Logic Journal a LATEST NEWS Tuesday, May 18, 2004 Eclipse II FPGA - Quicklogic Ships Industry's Lowest Power CPLD Alternative Altera Delivers World's Most Versatile Embedded Processor With Nios II Family Nios II Family Advances Altera's Opportunities in the Embedded Processor Market SBS Technologies Announces Next Generation of 1553 Conduction Cooled ASF Interface Boards Zaiq Technologies Adds SystemC Support to Its Seamlessly Retargetable System Verification Environment picoChip Demonstrates 'future-proof' WiMAX Modem; Software-upgradeable Solution for 802.16d and e reduces risk, Speeds Development and Accelerates Time-to-Market Xilinx FPGA Processor Solutions Deliver Order of Magnitude Advantage for Embedded Systems Designers Monday, May 17, 2004 Actel and Inicore Deliver Turnkey Design Solution to L-3 Targa Systems for Data Storage Products Universities Quick to Adopt Altium's Nexar Software; Interactive Design Methodology Enables Universities to Focus on Concepts Rather Than Software Magma Announces New Design Solutions for Low-cost Programmable IC Platforms; With Introduction of Blast FPGA and Blast SA, Magma Now Provides Full Spectrum of IC Design Solutions Friday, May 14, 2004 PLDApplications Partners With Denali for PCI Express Core Products Averant Announces a Significant Update to Solidify Thursday, May 13, 2004 Altera to Unveil Nios II Architecture at Embedded Processor Forum 2004 Ultra Data to Announce New Video Processor System for Advanced Codecs at Embedded Processor Forum Wednesday, May 12, 2004 MathStar Announces the 1 GHz Field Programmable Object Array (FPOA(TM)) Chip Family MathStar Attracts $9.6 Million to Support Introduction of 1 GHz FPOA(TM) Chips ANNOUNCEMENTS View the " Reduce Your System Costs: Design with New High-Density FPGAs " net seminar. This net seminar focuses on how to reduce your system costs and increase system performance with Altera's new StratixR II FPGA family. FS2 Introduces Altera Nios II In-Target System Analyzer. Now Available. OCIR (On-chip Instrumentation) provides powerful trace and triggering features for faster system and software debug and testing. Features -- 128K Trace Buffer, Bus Cycle Trace, Performance Analysis, Off-chip Trace. To order please visit www.fs2.com CURRENT FEATURE ARTICLES Packing Processor Power Altera Introduces Nios II The Next Implementation Fabric by Andrew B. Kahng, UCSD Board Roundup A Sampling of FPGA Development Boards Algorithms to Silicon ÿ Using Prototype Boards to Accelerate System-level Verification by Tom Feist, AccelChip Inc. DSP Heats Up Synplicity Enters DSP Synthesis From Gordon to Geoffrey Which Moore's the Law? A Matter of Integrity SI Issues Hit FPGAs on Board Fast and Accurate Multi-GigaHertz Modeling Techniques by Donald Telian, Cadence Design Systems, Inc. Upset with Neutrons Will SEUs hit the FPGA in your SUV? Cool in the Spotlight QuickLogic Focuses on Low Power a Packing Processor Power Altera Introduces Nios II Attention please! The days when embedded soft-core processors on FPGAs were novel little micro-controllers you could use instead of a hard-wired state machine are now officially over. Thank you. You could use Altera's new Nios II processor as a convenient replacement for a hard-wired state machine in your next FPGA design. You could also play Pong on your Pentium 4. In both cases, you'd be missing the point and serious under-utilizing your processor technology. This week, Altera announced the long-anticipated sequel to their popular Nios soft-core processor, and it is quite impressive. In short: Speed, flexibility and capability - up, size and cost - down. If you're a hardware designer, you may puzzle at the soft-core concept. Wouldn't hard-wired processors work better in the same way that hard-wired multipliers do? If you think that, bookmark this page, walk across the hall, and have a discussion with an embedded software developer. (They're really quite approachable and some of them even keep candy on their desks.) In case you couldn't locate a software engineer, here's a brief rundown. First, you only use a processor when you want it, and the FPGA vendor doesn't have to make the device more expensive by including hard-core processors that many customers will not need. Second, you only need to use enough resources to make the particular processor you need for your application. The new Nios-II family ranges from an "economy" version that consumes a miserly 500 logic elements (less than 20% of a low-cost Cyclone device), to a "fast" version (rated at over 200DMIPS on a Stratix II FPGA) that requires just over a thousand. Third, you can configure the processor to have just the special features you need without paying for what you don't need. With configurable caches, custom instructions and varying pipeline depths you can create a processor that is perfectly suited to your application. Finally, it may not be a question of which processor to use, but how many. With a 220DMIPS (fast) Nios II CPU requiring only 1% of a large Stratix II device, you can pile them on your FPGA like parmesan on pizza. It would be easy to evaluate Nios II in a vacuum, but failing to look at the bigger picture would sell short the potential of this powerful processing environment. In the larger context of FPGA-based reconfigurable computing, you can use parallel processing, custom instructions and hardware acceleration to push the performance of this platform into the stratosphere. For some applications, the combination of parallel Nios IIs running algorithms and control with hardware acceleration of math-intensive datapath processes (leveraging the built-in hardware multiply/accumulate resources of Stratix II) could drive your DMIPS off the map. [ more ] a The Next Implementation Fabric: Issues and Considerations by Andrew B. Kahng, Technical Program Co-Chair for Design Tools, 41st Design Automation Conference, Professor of CSE and ECE at the University of California, San Diego The semiconductor industry is caught on two horns of the economics dilemma: -- Technology scaling - sub-wavelength lithography, masks, and variability; and -- Design productivity - turnaround time, and reusability of design effort. Proliferation of semiconductors and their applications benefits from fast, cheap, and under-control ASIC-style implementation. Thus, the industry needs one or more implementation fabrics that support medium volume, lower cost, power and nonrecurring engineering (NRE) costs. To this end, several semiconductor technologies offer different visions of the next implementation fabric, as well as the application domains or cost-performance tradeoff points that such a fabric must support. On one end of the flexibility spectrum, FPGA vendors offer programmable ICs with highly regular switching and logic fabrics; these offer designers near-zero NRE costs, low design costs and fast turnaround times. The tradeoff is that FPGA fabrics incur higher unit costs, lower integration densities and operating frequencies, and increased power dissipation. [ more ] a a Visit Techfocus Media You're receiving this newsletter because you subscribed at our website www.fpgajournal.com . If someone forwarded this newsletter to you and you'd like to receive your own free subscription, go to: www.fpgajournal.com/update . If at any time, you would like to unsubscribe, send e-mail to unsubscribe@fpgajournal.com . (But we hope you don't.) If you have any questions or comments, send them to comments@fpgajournal.com . All material copyright c 2003-2004 techfocus media, inc. All rights reserved. Privacy Statement ÿ ÿ ÿ ÿ